IF age > 18 THEN
ALLOW_ACCESS = True
ELSE
ALLOW_ACCESS = False| Detail | Information |
|---|---|
| Name | Program Counter |
| Acronym | PC |
| What it holds | Memory address of the NEXT instruction to execute |
| How it works | Increments (adds 1) after each instruction |
| Example | PC=100 means "next instruction is at address 100" |
| After fetch | PC becomes 101, then 102, then 103... |
| Detail | Information |
|---|---|
| Name | Memory Address Register |
| Acronym | MAR |
| What it holds | Address of where to fetch data FROM memory |
| How it works | Sends address to Address Bus |
| Example | MAR=250 means "get data from memory location 250" |
| Used for | Telling memory which data to send |
| Detail | Information |
|---|---|
| Name | Memory Data Register |
| Acronym | MDR |
| What it holds | The actual data/instruction fetched from memory |
| How it works | Receives data via Data Bus from memory |
| Example | MDR receives "ADD 5, 3" from memory location 100 |
| Used for | Temporarily holding data from memory |
| Detail | Information |
|---|---|
| Name | Current Instruction Register |
| Acronym | CIR |
| What it holds | The instruction CPU is currently decoding/executing |
| How it works | Receives instruction from MDR |
| Example | CIR holds "ADD 5, 3" while CPU is working on it |
| Used for | Storing instruction during decode and execute |
| Detail | Information |
|---|---|
| Name | Accumulator |
| Acronym | ACC |
| What it holds | Results of calculations from ALU |
| How it works | ALU puts results here after math |
| Example | After 5 + 3 = 8, ACC stores "8" |
| Used for | Temporarily storing calculation results |
"[Register name] holds [what it stores],
which is used to [why/how it's used].""The MAR holds the memory address""The MAR holds the memory address of where data or instructions
are to be fetched from. This address is sent via the address bus
to memory so that the correct data can be retrieved."| Feature | Detail |
|---|---|
| Direction | UNIDIRECTIONAL (one way only) |
| Travels from | CPU to Memory |
| Carries | Memory addresses (locations) |
| Example | "Get data from location 200" |
| Width | 32-bit or 64-bit (determines how many addresses) |
| Analogy | Postal code - tells where to go |
| Feature | Detail |
|---|---|
| Direction | BIDIRECTIONAL (both ways) |
| Travels between | CPU ↔ Memory |
| Carries | Actual data AND instructions |
| Example | "Here is the instruction ADD 5, 3" |
| Width | 32-bit or 64-bit (determines how much data at once) |
| Analogy | Courier service - carries the actual package |
| Feature | Detail |
|---|---|
| Direction | BIDIRECTIONAL (both ways) |
| Travels between | CPU ↔ Components |
| Carries | Control signals and commands |
| Example | "Read from memory" or "Write to memory" |
| Types of signals | Read, Write, Interrupt, Clock signals |
| Analogy | Traffic lights - tells when to start/stop |
PC = 100 (says "I want instruction from location 100")
↓
MAR = 100 (copies the address)
↓
Address Bus sends: 100 to Memory
↓
Memory receives: "Find data at location 100"Control Unit sends signal: "READ from memory"
↓
Control Bus sends: READ command to Memory
↓
Memory receives: "Please send me the data"Memory finds instruction at location 100: "ADD 5, 3"
↓
Data Bus receives: "ADD 5, 3"
↓
MDR stores: "ADD 5, 3"
↓
CIR receives: "ADD 5, 3" (ready to decode)| Bus | Carries | Direction | Analogy |
|---|---|---|---|
| Address Bus | WHERE (location) | One-way | House address |
| Data Bus | WHAT (actual data) | Both ways | The actual letter |
| Term | Simple Meaning | Example |
|---|---|---|
| Von Neumann Architecture | Design showing how computer parts work together | All modern computers follow this |
| CPU | The processor that executes instructions | Intel Core i5, AMD Ryzen |
| Memory | Storage for programs and data | RAM (8GB, 16GB) |
| Register | Super-fast tiny storage inside CPU | Holds one instruction or number |
| Bus | Wires that carry data between components | Carries address, data, or control signals |
| Unidirectional | Can only go one way | Address Bus |
| Bidirectional | Can go both ways | Data Bus and Control Bus |
| Fetch | Get instruction from memory | First step of CPU cycle |
| Decode | Understand the instruction | Second step of CPU cycle |
| Execute | Perform the instruction | Third step of CPU cycle |
| Increment | Add 1 to a number | PC increments after each instruction |
| Component | Full Name | Holds What | Direction |
|---|---|---|---|
| PC | Program Counter | Next instruction address | - |
| MAR | Memory Address Register | Address to fetch from | Sends to bus |
| MDR | Memory Data Register | Instruction/Data from memory | Receives from bus |
| CIR | Current Instruction Register | Current instruction being decoded | - |
| ACC | Accumulator | Results from ALU | - |
| Address Bus | - | Memory locations | One-way (CPU→Memory) |
| Data Bus | - | Instructions and data | Both ways |
| Control Bus | - | Control signals | Both ways |